In an attempt to increase the performance of microprocessors with Static Random Access Memory (SRAM), many in the industry has developed microprocessors where the logic circuitry of the processor and the cache circuitry are placed in close proximity on the same substrate. The logic and cache circuitry are thus coupled.
FIG. 1 illustrates a cross section of a conventional microprocessor in which the logic and cache circuitry are placed on the same side of a substrate. The microprocessor 100 includes a substrate 110 on which contains the logic and cache circuitry 120 on one side of the substrate 110. On that same side, controlled collapsed chip connections 130 (commonly referred to as "C4"), encased in under fill, are attached between the substrate 110 and the substrate 140. The C4 facilitates the connections between the substrate 110 and one side of the substrate 140. C4 is well known in the art and will not be further described here. Heat generated by the circuitry on the substrate 110 is carried away in the opposite direction of the signal flow, from the logic and cache circuitry 120 to the pins, lands or balls. On the other side of the substrate 140, are pins 150, balls 160, and lands 170. The pins 150 attach the microprocessor 100 to a printed circuit board (not shown). Alternatively the balls 160 connect the microprocessor to printed circuit board. The lands 170 are landing pads which rests the microprocessor 100 upon the printed circuit board.
FIG. 2 illustrates a top view of the substrate 110 of the microprocessor 100. The logic and cache circuitry 120, are placed together in the center of the substrate 110. Decoupling capacitors 210 surround the circuitry to provide load energy/storage so that the electromagnetic fields created by the signals from the circuitry do not result in a draining of the distant power supply (not shown). The use of decoupling capacitors 210 are well known in the art and will not be further discussed here.
The coupling of the logic and cache circuitry 120 in the conventional microprocessor 100 allows recently used data or instructions in the cache to be readily available to the processor, instead of requiring the processor to search for the data or instructions as in the case where distant, slow Dynamic Random Access Memory (DRAM) is used. However, due to the coupling of the logic and cache circuitry 120, the "yield" of the substrate 110 is significantly reduced. What is meant by "yield" in the context of the present application is the total number of substrates that are viable on a wafer after the manufacturing process. As is well known in the art, the yield decreases exponentially as the area of the substrate increases if defect density is constant. In the microprocessor 100, since the logic and cache circuitry 120 are placed on the same side of the substrate, the required area of substrate 100 is larger as the logic and cache circuitry becomes larger. Thus, the yield for the microprocessor 100 suffers as the size of the logic and cache circuitry increases. Accordingly, the yield reliability and cost of the microprocessor 100 is adversely impacted.
Accordingly, there exists a need for a microprocessor which has the logic and cache circuitry in close proximity on the same substrate but which has a larger yield than conventional microprocessors. The present invention addresses such a need.